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Site-Competition Epitaxy Controls Doping of Silicon Carbide
(From the 1994 NASA Lewis Research & Technology Report)
Silicon carbide (SiC) is emerging as the material of choice for high-power and/or microwave-frequency semiconductor devices suitable for high-temperature, high radiation, and corrosive environments. Currently, the initial step in making SiC semiconductor devices is a process called chemical vapor deposition (CVD), which allows single-crystal layers (epilayers) of varying electrical character to be grown. The SiC epilayers are produced in the CVD process by thermally decomposing commercially available silicon and carbon source gases onto boule-derived SiC substrates. The electrical character is tailored by adding dopants, impurity elements that affect the epilayer electrical properties, during the CVD SiC epilayer growth by flowing either nitrogen (for n type) or trimethylaluminum (for p type). However, for the inherently superior high-temperature semiconductor properties of SiC to be realized in advanced electronic devices, control over the electronic properties of the CVD SiC epilayers must be improved.

Control over dopant incorporation for CVD SiC epilayers had been very limited. Reproducible doping was typically confined to a relatively narrow doping range, restricting SiC device performance to below theoretically predicted values. This narrow doping range was recently greatly expanded by the NASA Lewis discovery that the ratio of silicon source flow to carbon source flow during the CVD epilayer growth could be used to control dopant incorporation and therefore the electrical properties of the growing SiC epilayers. This process, named site-competition epitaxy, produces much lower doped SiC epilayers than was previously possible. In addition, site-competition epitaxy can produce more highly doped layers when more electrically conductive SiC epilayers are desired. Expanding the reproducible doping range to include lower concentrations has enabled the fabrication of multikilovolt SiC power devices, whereas the availability of higher doping concentrations has resulted in devices with improved performance because of lower parasitic resistances.

The site-competition epitaxy working model is based on the competition between the SiC and dopant source gases for the available substitutional lattice sites on the growing SiC crystal surface. Dopant incorporation is controlled by appropriately adjusting the Si/C ratio within the growth reactor to affect the amount of dopant atoms incorporated into these sites, either carbon-lattice sites (C sites) or silicon lattice sites (Si sites), located on the active growth surface of the SiC crystal. Specifically, our model for site-competition epitaxy is based on the principle of competition between nitrogen and carbon for the C sites and between aluminum and silicon for the Si sites of the growing SiC epilayer. The concentration of n-type (nitrogen) dopant atoms, which can occupy only C sites, incorporated into a growing SiC epilayer can be decreased by increasing the carbon source concentration "out competes" N for the available C sites.

In summary, the nitrogen donor concentration in the grown epilayer is proportional to the Si/C ratio during epilayer growth, whereas the aluminum acceptor concentration is inversely proportional to the Si/C ratio. Site competition epitaxy was used (as depicted) to produce the very low-doped epilayers required for the world's first 6H-SiC 2000-V and 3C-SiC 300-V diodes. More recently, this novel growth technique has enabled the fabrication of SiC junction field-effect transistors (JFET's) that can operate at 600 C in air for 30 hr. The site-competition epitaxy technique not only greatly expands the doping range for SiC but also allows for more reproducible dopant control within the previously attainable doping range. Additionally, site-competition epitaxy is the only known route for growing degenerately doped epilayers that result in ohmic as-deposited (i.e., unannealed) contacts for a variety of metals on both p-type and n-type SiC epilayers.

This work was performed in-house as part of the High-Temperature Integrated Electronics and Sensors (HTIES) Program at NASA Lewis. U.S. Patent 5,463,978 covering this technology was awarded November 7, 1995.
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