All spacecraft use networks of wires to transport commands and data between subsystems. Data networks onboard current spacecraft are generally standardized on a MIL-STD-1553/1773 bus with the Consultative Committee for Space Data Systems (CCSDS) protocol, which has a maximum speed of 1 Mbps. This is sufficient to pass commands from command and data handling (C&DH) to the various subsystems onboard the spacecraft, with a couple hundred kilobits available to transport science data from instruments to the downlink or mass storage. In addition to the 1553/1773 harness, there are usually custom discrete harnesses of up to hundreds of wires to transport high-speed data around the spacecraft. The custom harnesses add tens of kilograms, tens of watts, and complexity to the overall payload design. The current spacecraft network architecture dates back decades, and in the interim, ground-based commercial networks using new data protocols and physical layers have exploded in capability with multi-gigabit networks now commonplace in long-haul applications, Also, the CCSDS protocols used in current spacecraft are not compatible with commercial ground networks.
The overall objective of this research was to develop low-power, miniaturized, high-data-rate onboard networking technology for distributed communications based on standards that would be beneficial to high-data-rate programs such as the National Polar Orbiting Operational Environmental Satellite System (NPOESS), Geostationary Operational Environmental Satellite Program R Series (GOES-R), Lunar Reconnaissance Orbiter, Space Interferometry Mission, James Webb Space Telescope, and others. The project addresses the development and delivery of prototype SpaceWire bus Application Specific Integrated Circuit (ASIC) chips capable of >100 Mbps throughput. The SpaceWire ASIC achieved 260 MHz, or 260 Mbps raw data rate, which is at least an order of magnitude increase in the current state of the art for spacecraft bus data rates. Also, the SpaceWire ASIC represents an innovative approach to solving onboard network communication. Integrating the input/output interface with a complete system on a single chip (microcontroller, memory subsystem, back panel interface Peripheral Component Interconnect (PCI), direct memory access (DMA) controller, programmable input/output, timers, four SpaceWire ports, and a router), the SpaceWire ASIC achieves a high level of capability and density not obtainable in previous technologies.
The SpaceWire ASIC was successfully developed and tested under contract by BAE Systems in Manassas, Virginia, and delivered to the NASA Glenn Research Center in December 2005.
BAE Spacewire ASIC.
At least two NASA programs have applied this new technology to their missions. The C&DH subsystem of the Lunar Reconnaissance Orbiter will baseline the SpaceWire ASIC, and the orbiter’s single board computer will use it to communicate with various other subsystems.
Lunar Reconnaissance Orbiter processor board with SpaceWire ASIC. SRAM, static random access memory.
The GOES-R weather satellite is being developed jointly by NASA and the National Oceanic and Atmospheric Administration. The satellite has a complement of four instrument suites ranging from 200 Kbps to 65 Mbps. The SpaceWire design will be used as a primary interface for C&DH and science data. A prototype board was tested, and the ASIC’s functionality and performance was verified.
Jones, Robert E.: Design and Characterization of a State-of-the-Art High Speed Payload Interface Device for Use on Satellites Using RAD Hard Technology Based on Spacewire. Contract number NAS3-03086, 2003.
Glenn contact: Nam T. Nguyen, 216-433-3425, Nam.T.Nguyen@nasa.govLast updated: December 14, 2007
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