Nanometer Step Height Standard artifact chip developed to enable greatly improved calibration of scanning probe microscopy instruments. The small SiC chip (seen on the fingertip) contains an array of over 100 step pyramids (like those shown in the highly magnified atomic force microscope image inset) with highly repeatable 1.0-nm height steps produced by high-temperature growth and etching of SiC mesas.
NASA Glenn Research Center engineers, in collaboration with Sest, Inc., and the Ohio Aerospace Institute (OAI), have developed a greatly improved diagnostic tool to evaluate and verify the operation and calibration of scanning probe microscopy (SPM) instruments used for measuring nanoscale objects, meeting a vitally important need for the nanotechnology field that is expected to grow dramatically over the next decade. The Nanometer Step Height Standard is a calibration standard chip made of single-crystal silicon carbide (SiC). The small SiC chip (seen on the fingertip in the photograph) contains an array of over 100 step pyramids like those shown in the highly magnified atomic force microscope image of the photograph inset. Each side of the nanoscale step pyramid features regularly spaced steps nearly 1-μm apart, with atomically flat terraces between step risers of either 0.5 or 1.0 nm in height, as chosen during fabrication. These step heights are around 10 times smaller than those of previous standards for SPM instrument calibration. The height of the steps is directly linked to the atomic spacing of the atoms in the SiC crystal structure, which is a well-known physical constant. Therefore, unlike previous standards, the SiC Nanometer Step Height Standards do not have the expensive and time-consuming requirement to be individually calibrated and certified by the National Institute of Standards and Technology (NIST).
The nanoscale step structures are produced on the top surfaces of commercial SiC wafers using conventional microelectronics photolithographic patterning and reactive ion etching processes, followed by high-temperature(>1000 °C) SiC epitaxial growth and etching pioneered by the Glenn research team. This process enables hundreds of calibration step structures to be mass-produced on a single SiC wafer, which should greatly increase the availability and affordability of precision SPM calibration for microtechnologies and nanotechnologies worldwide.
Find out more about silicon carbide electronics at Glenn: http://www.grc.nasa.gov/WWW/SiC
Dr. Philip G. Neudeck, 216-433-8902, Philip.G.Neudeck@nasa.gov; and Dr. Phillip B. Abel, 216-433-6063, Phillip.B.Abel@nasa.gov
Sest, Inc., contact: J. Anthony Powell, 216-433-3652, J.A.Powell@nasa.gov
Ohio Aerospace Institute (OAI) contact: Andrew J. Trunek, 216-433-6736, Andrew.J.Trunek@nasa.gov
Authors: Dr. Philip G. Neudeck, Dr. Phillip B. Abel, J. Anthony Powell, and Andrew J. Trunek
Headquarters program office: Aeronautics Research
Special recognition: 2004 R&D 100 Award Winner, U.S. Patent 6,869,480
Last updated: October 16, 2006
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