SEM image of a microscale tensile test specimen in the process of fabrication using
SF6 and Ar plasma. Single-crystal SiC has been etched to a depth of 80 μm.
Silicon carbide (SiC) is a promising material for harsh environment sensors and electronics because it can enable such devices to withstand high temperatures and corrosive environments. Microfabrication techniques have been studied extensively in an effort to obtain the same flexibility of machining SiC that is possible for the fabrication of silicon devices. Bulk micromachining using deep reactive ion etching (DRIE) is attractive because it allows the fabrication of microstructures with high aspect ratios (etch depth divided by lateral feature size) in single-crystal or polycrystalline wafers. Previously, the Sensors and Electronics Branch of the NASA Glenn Research Center developed a DRIE process for SiC using the etchant gases sulfur hexafluoride (SF6) and argon (Ar) (ref. 1). This process provides an adequate etch rate of 0.2 μm/min and yields a smooth surface at the etch bottom. However, the etch sidewalls are rougher than desired, as shown in the preceding photomicrograph. Furthermore, the resulting structures have sides that slope inwards, rather than being precisely vertical. A new DRIE process for SiC was developed at Glenn that produces smooth, vertical sidewalls, while maintaining an adequately high etch rate.
A time-multiplexed etch-passivate (TMEP) process is widely used in the DRIE of silicon in forming structures with aspect ratios greater than 30. This technique alternates fluorine-plasma etching of the substrate with the deposition of a passivating polymer layer to produce an anisotropic profile (i.e., vertical sidewalls). Without TMEP, high rates of lateral etching occur because of the high reactivity of silicon with fluorine radicals, which causes the etch mask to be undercut and reduces the aspect ratio attainable. On the other hand, SiC is relatively inert, and appreciable etch rates using a fluorine plasma are obtained only when the SiC surface is subjected to ion bombardment. Since the ions are well collimated and strike only the horizontal surfaces of the substrate, the SiC etch process is inherently anisotropic. The lateral etch rate, however, while small, is not zero, which roughens the sidewalls.
By utilizing a TMEP process, Glenn researchers have been able to control the roughness and slope of the sides of etched SiC features. An etch mask of electroplated nickel is used to selectively protect areas of the wafer. SF6 is used as the etching gas, and octafluorocyclobutane (C4F8) is used to deposit a fluorocarbon polymer film that protects the sidewalls from lateral etching. Scanning electron microscope (SEM) images of patterned features demonstrate smooth, vertical sidewalls (see the following photomicrograph). Depths of 150 μm have been achieved with dimensions as low as 50 μm. Further development of the process is expected to enable the fabrication of high-aspect-ratio structures in SiC with smooth sidewalls.
SEM image of a microscale tensile test specimen fabricated using a TMEP process.
A single-crystal SiC wafer with a thickness of 135 μm has been etched entirely
through.
Find out more about this research.
Glenn contacts: Laura Evans, 216-433-9845, Laura.J.Evans@nasa.gov; and Dr. Glenn Beheim, 216-433-3847, Glenn.M.Beheim@grc.nasa.gov
Authors: Laura J. Evans and Dr. Glenn M. Beheim
Headquarters program office: OAT
Programs/Projects: AEFT
Last updated: July 18, 2005 10:00 AM
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